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1 low-noise 24-bit delta sigma adc ISL26132, isl26134 the ISL26132 and isl26134 are complete analog front ends for high resolution measuremen t applications. these 24-bit delta-sigma analog-to-digital converters include a very low-noise amplifier and are avai lable as either two or four differential multiplexer inputs. the devices offer the same pinout as the ads1232 an d ads1234 devices and are functionally compatible with these devices. the ISL26132 and isl26134 offer improved nois e performance at 10sps and 80sps conversion rates. the on-chip low-noise programm able-gain amplif ier provides gains of 1x/2x/64x/128x. the 128x gain setting provides an input range of 9.766mvfs when using a 2.5v reference. the high input impedance allows dire ct connection of sensors such as load cell bridges to ensure the specified measurement accuracy without additional circui try. the inputs accept signals 100mv outside the supply rails when the device is set for unity gain. the delta-sigma adc features a third order modulator providing up to 21.6-bit noise-free performance. the device can be operated fr om an external clock source, crystal (4.9152mhz typical), or the on-chi p oscillator. the two channel ISL26132 is available in a 24 ld tssop package and the four channel is l26134 is available in a 28 ld tssop package. both are specified for operation over the automotive temperature range (-40c to +105c). features ? up to 21.6 noise-free bits. ? low noise amplifier with gains of 1x/2x/64x/128x ? rms noise: 10.2nv @ 10sps (pga = 128x) ? linearity error: 0.0002% fs ? simultaneous rejection of 50hz and 60hz (@ 10sps) ? two (ISL26132) or four (isl 26134) channel differential input multiplexer ? on-chip temperature sensor (ISL26132) ? automatic clock source detection ? simple interface to read conversions ? +5v analog, +5 to +2.7v digital supplies ? pb-free (rohs compliant) ? tssop packages: ISL26132, 24 pin; isl26134, 28 pin applications ?weigh scales ? temperature monitors and controls ? industrial process control ? pressure sensors adc pga 1x/2x/64x/ 128x internal clock sdo/rdy sclk dvdd avdd dgnd agnd xtalin/clock vref+ external oscillator xtalout vref- a0 a1/temp ain1+ ain1- ain2+ ain2- ain3+ ain3- ain4+ ain4- input multiplexer isl26134 only cap cap gain1 gain0 pwdn speed dgnd dgnd note for a1/temp pin: functions as a1 on isl26134; functions as temp on ISL26132 figure 1. block diagram september 9, 2011 fn6954.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL26132, isl26134 2 fn6954.1 september 9, 2011 ordering information part number (notes 2, 3) part marking temperature range (c) package (pb-free) pkg. dwg number ISL26132avz 26132 avz -40 to +105 24 ld tssop m24.173 ISL26132avz-t (note 1) 26132 avz -40 to +105 24 ld tssop (tape & reel) m24.173 ISL26132avz-t7a (note 1) 26132 avz -40 to +105 24 ld tssop (tape & reel) m24.173 isl26134avz 26134 avz -40 to +105 28 ld tssop m28.173 isl26134avz-t (note 1) 26134 avz -40 to +105 28 ld tssop (tape & reel) m28.173 isl26134avz-t7a (note 1) 26134 avz -40 to +105 28 ld tssop (tape & reel) m28.173 isl26134av28ev1z evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL26132 , isl26134 . for more information on msl please see techbrief tb363 . table 1. key differences of parts part number number of channels on-chi p temperature sensor number of pins ISL26132 2 yes 24 isl26134 4 no 28 pin configurations ISL26132 (24 ld tssop) top view isl26134 (28 ld tssop) top view 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 dvdd dgnd xtalin/clock xtalout dgnd dgnd temp a0 cap cap ain1+ ain1- sdo/rdy pdwn speed gain1 gain0 agnd vref- ain2+ ain2- sclk avdd vref+ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 dvdd dgnd xtalin/clock xtalout dgnd dgnd a1 a0 cap cap ain1+ ain1- ain3+ ain3- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 sdo/rdy pdwn speed gain1 gain0 agnd vref- ain2+ ain2- ain4+ ain4- sclk avdd vref+
ISL26132, isl26134 3 fn6954.1 september 9, 2011 pin descriptions name pin number analog/digital input/output description ISL26132 isl26134 dvdd 1 1 digital digital power supply (2.7v to 5.25v) dgnd 2, 5, 6 2, 5, 6 digital digital ground xtalin/clock 3 3 digital/digital input external clock input: typically 4.9152mhz. tie low to activate internal oscillator. can also use external crystal across xtalin/clock and xtalout pins. xtalout 4 4 digital external crystal connection temp 7 - digital input on-chip temperature diode enable a1 a0 - 8 7 8 digital input cap 9, 10 9, 10 analog pga filter capacitor ain1+ 11 11 analog input positive analog input channel 1 ain1- 12 12 analog input negative analog input channel 1 ain3+ - 13 analog input positive analog input channel 3 ain3- - 14 analog input negative analog input channel 3 ain4- - 15 analog input negative analog input channel 4 ain4+ - 16 analog input positive analog input channel 4 ain2- 13 17 analog input negative analog input channel 2 ain2+ 14 18 analog input positive analog input channel 2 vref- 15 19 analog input negative reference input vref+ 16 20 analog input positive reference input agnd 17 21 analog analog ground avdd 18 22 analog analog power supply 4.75v to 5.25v gain0 gain1 19 20 23 24 digital input table 2. input multiplexer select isl26134 ISL26132 a1 a0 channel 00ain1 01ain2 10ain3 11ain4 table 3. gain select gain1 gain0 gain 001 012 1064 11128
ISL26132, isl26134 4 fn6954.1 september 9, 2011 circuit description the ISL26132 (2-channel) and isl26134 (4-channel) devices are very low noise 24-bit delta-sigma adcs that include a programmable gain amplifier and an input multiplexer. the ISL26132 offers an on-chi p temperature measurement capability. the ISL26132, isl26134 provide pin compatibility and output data compatibility with the ads1232/ads1234, and offer the same conversion rates of 10sps and 80sps. all the features of the ISL26132, isl26134 are pin-controllable, while offset calibration, standby mode, and output conversion data are accessible through a simple 2-wire interface. the clock can be selected to come from an internal oscillator, an external clock signal, or crystal (4.9152mhz typical). speed 21 25 digital input pdwn 22 26 digital input power-down: holding this pin low powers down the entire converter and resets the adc. sclk 23 27 digital input serial clock: clock out data on the rising edge. also used to initiate offset calibration and sleep modes. see ?serial clock input (sclk)? on page 14 for more details. sdo/rdy 24 28 digital output dual-purpose output: data ready: indicate valid data by going low. data output: outputs data, msb first, on the first rising edge of sclk. pin descriptions (continued) name pin number analog/digital input/output description ISL26132 isl26134 table 4. data rate select speed data rate 010sps 1 80sps
ISL26132, isl26134 5 fn6954.1 september 9, 2011 absolute maximum rating s thermal information a gnd to d gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v analog in to a gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to a vdd +0.3v digital in to d gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to d vdd +0.3v input current momentary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ma continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma esd rating human body model (per mil-std-883 method 3015.7) . . . . . . . . . . . . .7.5kv machine model (per jesd22-a115). . . . . . . . . . . . . . . . . . . . . . . . . . 450v charged device model (per jesd22-c101) . . . . . . . . . . . . . . . . . . . . . . . . 2kv latch-up (per jedec jesd -78b; class 2, level a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ma @ room and hot (+105c) thermal resistance (typical) ja (c/w) jc (c/w) 24 ld tssop (notes 4, 5) . . . . . . . . . . . . . . 65 18 28 ld tssop (notes 4, 5) . . . . . . . . . . . . . . 63 18 maximum power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mw maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c a vdd to a gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.75v to 5.25v d vdd to d gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.25v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for jc , the ?case temp? location is taken at the package top center. electrical specifications v ref + = 5v, v ref - = 0v, a vdd = 5v, d vdd = 5v, a gnd = d gnd = 0v, mclk = 4.9152mhz, and t a = -40c to +105c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +105c symbol parameter test level or notes min (note 6) typ max (note 6) units analog inputs differential input voltage range 0.5v ref / gain v common mode input voltage range gain = 1, 2 a gnd - 0.1 a vdd + 0.1 v gain = 64, 128 a gnd +1.5 a vdd - 1.5 v differential input current gain = 1 20 na gain = 2 40 na gain = 64, 128 1 na system performance resolution no missing codes 24 bits data rate internal osc. speed = high 80 sps internal osc. speed = low 10 sps external osc. speed = high fclk/61440 sps external osc. speed = low fclk/49152 0 sps digital filter settling time full setting 4 conversions inl integral nonlinearity differential input gain = 1, 2 0.0002 0.001 % of fsr (note 7) differential input gain = 64, 128 0.0004 % of fsr (note 7) input offset error gain = 1 0.4 ppm of fs gain = 128 1.5 ppm of fs input offset drift gain = 1 0.3 v/ c gain = 128 10 nv/c gain error (note 8) gain = 1 0.007 0.02 % gain = 128 0.02 % gain drift gain = 1 0.5 ppm/ c gain = 128 7 ppm/ c
ISL26132, isl26134 6 fn6954.1 september 9, 2011 cmrr common mode rejection at dc, gain = 1, v = 1v 85 100 db at dc, gain = 128, v = 0.1v 100 db 50hz/60hz rejection (note 9) ex ternal 4.9152mhz clock 130 db psrr power supply rejection at dc, gain = 1, v = 1v 82 100 db at dc, gain = 128, v = 0.1v 100 105 db input referred noise see ?typical characteristics? beginning on page 8 noise free bits see ?typical characteristics? beginning on page 8 voltage reference input vref voltage reference input vref = vref+ - vref- 1.5 avdd avdd + 0.1 v vref- negative reference input agnd - 0.1 vref+ - 1.5 v vref+ positive reference input vref- + 1.5 avdd + 0.1 v iref voltage reference input current 350 na power supply requirements a vdd analog supply voltage 4.75 5.0 5.25 v d vdd digital supply voltage 2.7 3.3 5.25 v a idd analog supply current normal mode, avdd = 5, gain = 1, 2 7 8.5 ma normal mode, avdd = 5, gain = 64, 128 9 12 ma standby mode 0.2 3 a power-down 0.2 2.5 a d idd digital supply current normal mode, avdd = 5, gain = 1, 2 750 950 a normal mode, avdd = 5, gain = 64, 128 750 950 a standby mode 1.5 26 a power-down 1 26 a p d power dissipation, total normal mode, avdd = 5, gain = 1, 2 49.6 mw normal mode, avdd = 5, gain = 64, 128 68 mw standby mode 0.14 mw power-down 0.14 mw digital inputs v ih 0.7 d vdd v v il 0.2 d vdd v v oh i oh = -1ma d vdd - 0.4 v v ol i ol = 1ma 0.2 d vdd v input leakage current 10 a external clock input frequency 0.3 4.9152 mhz serial clock input frequency 1 mhz note: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. 7. fsr = full scale range = vref/gain 8. gain accuracy is calibrated at the factory (avdd = +5v). 9. specified for word rate equal to 10sps. electrical specifications v ref + = 5v, v ref - = 0v, a vdd = 5v, d vdd = 5v, a gnd = d gnd = 0v, mclk = 4.9152mhz, and t a = -40c to +105c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +105c (continued) symbol parameter test level or notes min (note 6) typ max (note 6) units
ISL26132, isl26134 7 fn6954.1 september 9, 2011 noise performance the ISL26132 and isl26134 provide excellent noise performance. the noise performance on each of the gain settings of the pga at the selected word rates is shown in tables 5 and 6. resolution in bits decreases by 1- bit if the adc is operated as a single-ended input device. noise measurements are input-referred, taken with bipolar inputs under the specified operating conditions, with f clk = 4.9152mhz. table 5. a vdd = 5v, v ref = 5v, data rate = 10sps gain rms noise (nv) peak-to-peak noise (nv) (note 10) noise-free bits (note 11) 1 243 1604 21.6 2 148 977 21.3 64 10.8 71 20.1 128 10.2 67 19.1 table 6. a vdd = 5v, v ref = 5v, data rate = 80sps gain rms noise (nv) peak-to-peak noise (nv) (note 10) noise-free bits (note 11) 1 565 3730 20.4 2 285 1880 20.3 64 28.3 187 18.7 128 27 178 17.7 notes: 10. the peak-to-peak noise number is 6.6 times the rms value. this encompasses 99.99% of the noise ex cursions that may occur. this value best represents the worst case noise that could occur in the output conversion words from the converter. 11. noise-free bits is defined as: no ise-free bits = ln(fsr/peak-to-peak noise)/ln(2) where fsr is the full scale range of the converter, vref/gain.
ISL26132, isl26134 8 fn6954.1 september 9, 2011 typical characteristics figure 2. noise at gain = 1, 10sps figure 3. noise histogram at gain = 1, 10sps figure 4. noise at gain = 2, 10sps figure 5. noise histogram at gain = 2, 10sps figure 6. noise at gain = 64, 10sps figure 7. noise histogram at gain = 64, 10sps -10 -5 0 5 10 0 200 400 600 800 1000 gain = 1 rate = 10sps time (samples) output code (lsb) 0 50 100 150 200 250 300 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 output code (lsb) gain = 1, n = 1024 rate = 10sps std dev = 1.635 lsb vref = 2.5v counts -10 -5 0 5 10 0 200 400 600 800 1000 time (samples) output code (lsb) gain = 2 rate = 10sps 0 50 100 150 200 250 -8 -6 -4 -2 0 2 4 6 8 gain = 2, n = 1024 rate = 10sps std dev = 1.989 lsb vref = 2.5v output code (lsb) counts -15 -10 -5 0 5 10 15 20 0 200 400 600 800 1000 time (samples) output code (lsb) gain = 64 rate = 10sps 0 20 40 60 80 100 120 -20 -15 -10 -5 0 5 10 15 20 gain = 64, n = 1024 rate = 10sps std dev = 4.627 lsb vref = 2.5v output code (lsb) counts
ISL26132, isl26134 9 fn6954.1 september 9, 2011 figure 8. noise at gain = 128, 10sps figure 9. noise histogram at gain = 128, 10sps figure 10. noise at gain = 1, 80sps figure 11. noise histogram at gain = 1, 80sps figure 12. noise at gain = 2, 80sps figure 13. noise histogram at gain = 2, 80sps typical characteristics (continued) -50 -30 -10 10 30 50 0 200 400 600 800 1000 gain = 128 rate = 10sps time (samples) output code (lsb) 0 10 20 30 40 50 60 -30-25-20-15-10-5 0 5 1015202530 output code (lsb) counts gain = 128, n = 1024 rate = 10sps std dev = 8.757 lsb vref = 2.5v -25 -20 -15 -10 -5 0 5 10 15 20 25 0 200 400 600 800 1000 gain = 1 rate = 80sps time (samples) output code (lsb) 0 20 40 60 80 100 120 -15 -10 -5 0 5 10 15 output code (lsb) counts gain = 1, n = 1024 rate = 80sps std dev = 3.791 lsb vref = 2.5v -25 -15 -5 5 15 25 0 200 400 600 800 1000 gain = 2 rate = 80sps time (samples) output code (lsb) 0 20 40 60 80 100 120 -15 -10 -5 0 5 10 15 output code (lsb) counts gain = 2, n = 1024 rate = 80sps std dev = 3.831 lsb vref = 2.5v
ISL26132, isl26134 10 fn6954.1 september 9, 2011 figure 14. noise at gain = 64, 80sps figu re 15. noise histogram at gain = 64, 80sps figure 16. noise at gain = 128, 80sps figure 17. noise histogram at gain = 128, 80sps figure 18. analog current vs temperature figure 19. digital current vs temperature typical characteristics (continued) -100 -50 0 50 100 0 200 400 600 800 1000 gain = 64 rate = 80sps time (samples) output code (lsb) 0 10 20 30 40 50 -40-35-30-25-20-15-10-5 0 5 10152025303540 output code (lsb) counts gain = 64, n = 1024 rate = 80sps std dev = 12.15 lsb vref = 2.5v -200 -160 -120 -80 -40 0 40 80 120 160 0 200 400 600 800 1000 gain = 128 rate = 80sps time (samples) output code (lsb) 0 5 10 15 20 25 30 -80 -60 -40 -20 0 20 40 60 80 output code (lsb) counts gain = 128, n = 1024 rate = 80sps std dev = 23.215 lsb vref = 2.5v 0 2 4 6 8 10 -40 -10 20 50 80 110 temperature (c) current (ma) normal mode, pga = 64.128 normal mode, pga = 1, 2 1 10 100 1000 10000 -40 -10 20 50 80 110 temperature (c) current (a) normal mode, all pga gains powerdown mode
ISL26132, isl26134 11 fn6954.1 september 9, 2011 figure 20. typical word rate vs temperature using internal oscillator figure 21. noise density vs frequency at gain = 1, 80sps figure 22. noise density vs frequency at gain = 128, 80sps typical characteristics (continued) 9.6 9.8 10.0 10.2 10.4 10.6 10.8 11.0 -40 -10 20 50 80 110 temperature (c) data rate (sps) word rate = 10sps 10 100 1000 10000 0.01 0.1 1 10 frequency (hz) noise (nv/ hz) gain = 1, 80sps 64k fft 25 averages 1 10 100 0.01 0.1 1 10 frequency (hz) noise (nv/ hz) gain = 128, 80sps 64k fft 25 averages
ISL26132, isl26134 12 fn6954.1 september 9, 2011 functional description analog inputs the analog signal inputs to th e ISL26132 connect to a 2-channel differential multiplexer and the isl26134 connect to a 4-channel differential multiplexer (mux). the multiplexer connects a pair of inputs to the positive and negative inputs (ainx+, ainx-), selected by the channel select pins a0 and a1 (isl26134 only). input channel selection is shown in table 7. on the ISL26132, the temp pin is used to select the temperature sensor function. whenever the mux channel is ch anged (i.e. if any one of the following inputs - a0/a1, gain1/0, speed is changed), the digital logic will automatically restart the digital filter and will cause sdo/rdy to go low only when the output is fully settled. but if the input itself is suddenly changed, then the user needs to ignore first four rdy pulses (going low) to get an accurate measurement of the input signal. the input span of the adc is 0.5 vref/gain. for a 5v vref and a gain of 1x, the input span will be 5v p-p fully differential as shown in figure 23. note that input voltages that exceed the supply rails by more than 100mv will turn on the esd protection diodes and degrade measurement accuracy. if the differential input exceeds well above the +ve or the -ve fs (by ~1.5x times) the output code will clip to the corresponding fs value. under such conditions, th e output data rate will become 1/4th of the original value as the digital state machine will reset the delta-sigma modulato r and the decimation filter. temperature sensor (ISL26132 only) when the temp pin of the ISL26132 is set high, the input multiplexer is connected to a pair of diodes, which are scaled in both size and current. the voltage difference measured between them corresponds to the temper ature of the die according to equation 1: note: valid only for gain = 1x or 2x where t is the temperature of the die, and gain = the pga gain setting. at a temperature of +25c, the measured voltage will be approximately 111.7mv. note that this measurement indicates only the temperature of the die itself. applying the result to correct for the temperature drift of a device external to the package requires that thermal coupling between the sensor and the die be taken into account. low-noise programmable gain amplifier (pga) the chopper-stabilized programmab le gain amplifier features a variety of gain settings to achieve maximum dynamic range and measurement accuracy from popular sensor types with excellent low noise performance, input offset error, and low drift, and with minimal external parts count. the gain0 and gain1 pins allow the user to select gain settings of 1x , 2x, 64x, or 128x. a block diagram is shown in figure 24. the differential input stage provides a gain of 64, which is bypassed when the lower gain settings are selected. the lower gain settings (1 and 2) will accept inputs with common mode voltages up to 100mv outside the rails, allowing the device to accept ground-referred signals. at gain settings of 64 or 128 the common mode voltage at the inputs is limited to 1.5v inside the supply rails while maintaining specified measurement accuracy. table 7. input channel selection channel select pins analog input pins selected a1 a0 ain+ ain- 00ain1+ ain1- 01ain2+ ain2- 10ain3+ ain3- 11ain4+ ain4- 3.75 2.50 1.25 1.25v input voltage range = 0.5vref/gain vref = 5v, gain = 1x 3.75 2.50 1.25 ain+ ain- 2.50v figure 23. differential input for vref = 5v, gain = 1x v102.2mv(379 v + = ? t c () ) ? gain (eq. 1)
ISL26132, isl26134 13 fn6954.1 september 9, 2011 filtering pga output noise the programmable gain amplifier, as shown in figure 24, includes a passive rc filter on its output. the resistors are located inside the chip on the outputs of the differential amplifier stages. the capacitor (nominally a 100nf c0g ceramic or a pps film (polyphenylene sulfide)) for the filter is connected to the two cap pins of the chip. the output s of the differential amplifier stages of the pga are filtered before their signals are presented to the delta-sigma modulator. this filter reduces the amount of noise by limiting the signal band width and filters the chopping artifacts of the chopped pga stage. voltage reference inputs (vref+, vref-) the voltage reference for the adc is derived from the difference in the voltages presented to the vref+ and vref- pins; vref = (vref+ - vref-). the adcs are specified with a voltage reference value of 5v, but a voltage reference as low as 1.5v can be used. for proper operation, the voltage on the vref+ pin should not be greater than avdd + 0.1v and the voltage on the vref- pin should not be more negative than agnd - 0.1v. clock sources the ISL26132, isl26134 can operate from an internal oscillator, an external clock source, or fr om a crystal connected between the xtalin/clock and xtalout pi ns. see the block diagram of the clock system in figure 25. when the adc is powered up, the clock detect block determines if an external clock source is present. if a clock greater than 300khz is present on the xtalin/clock pin, the circuitry will disable the internal oscillator on the chip and use the external clock as the clock to drive the chip circuitry. if the adc is to be operated from the internal oscillator, the xtalin/clock pin should be grounded. if the adc is to be operated from a crystal, it should be located close to the package pins of the adc. note that external loading capacitors for the crystal are no t required as there are loading capacitors built into the silicon, although the capacitor values are optimized for operation with a 4.9152mhz crystal. the xtalout pin is not intended to drive external circuits. digital filter characteristics the digital filter inside the adc is a fourth-order siinc filter. figures 26 and 27 illustrate the filter response for the adc when it is operated from a 4.9152mhz crystal. the internal oscillator is factory trimmed so the frequency re sponse for the filter will be much the same when using the internal oscillator. the figures illustrate that when the converter is operated at 10sps the digital filter provides excellent rejection of 50hz and 60hz line interference. figure 24. simplified programmable gain amplifier block diagram + - a1 - + a2 ainx- ainx+ adc r int r int r 1 r f1 r f2 cap cap figure 25. clock block diagram xtalin/ crystal oscillator xtalout to adc internal oscillator clock detect mux en clock
ISL26132, isl26134 14 fn6954.1 september 9, 2011 serial clock input (sclk) the serial clock input is provided with hysteresis to minimize false triggering. nevertheless, care should be taken to ensure reliable clocking. filter settling time and adc latency whenever the analog signal into the ISL26132, isl26134 converters is changed, the effect s of the digital filter must be taken into account. the filter ta kes four data ready periods for the output code to fully reflect a new value at the analog input. if the multiplexer control input is changed, the modulator and the digital filter are reset, and the device uses four data ready periods to fully settle to yield a digital code that accurately represents the analog input. therefore, from the time the control inputs for the multiplexer are changed until the sdo/rdy goes low, four data ready periods will elapse. the settling time delay after a multiplexer channel change is listed in table 8 for the converter operating in cont inuous conversion mode. 0 -50 -100 -150 0 102030405060708090100 frequency (hz) gain (db) data rate = 10 sps data rate = 10sps figure 26. 10sps: frequency response out to 100hz -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 45 50 55 60 65 frequency (hz) gain (db) data rate = 10sps figure 27. 10sps: 50/60hz noise rejection, 45hz to 65hz table 8. settling time parameter description (f clk = 4.9152mhz) min max units t s a0, a1, speed, gain1, gain0 change set-up time 40 50 s t1 settling time speed = 1 54 55 ms speed = 0 404 405 ms figure 28. sdo/rdy delay after multiplexer change sdo/rdy t s t 1 a0, a1, speed, gain1, gain0
ISL26132, isl26134 15 fn6954.1 september 9, 2011 conversion data rate the speed pin is used to select between the 10sps and 80sps conversion rates. the 10sps rate (speed = low) is preferred in applications requiring 50/60hz no ise rejection. note that the sample rate is directly related to the oscillator frequency, as 491,520 clocks are required to perform a conversion at the 10sps rate, and 61,440 clocks at the 80sps rate. output data format the 24-bit converter output word is delivered in two?s complement format. input exceeding full scale results in a clipped output which will not return to in-range values until after the input signal has returned to the specified allowable voltage range and the digital filter has settled as discussed previously. reading conversion data from the serial data output/ready sdo/rdy pin when the adc is powered, it will automatically begin doing conversions. the sdo/rdy signal will go low to indicate the completion of a conversion. after the sdo/rdy signal goes low, the msb data bit of the conversion word will be output from the sdo/rdy pin after sclk is transitioned from a low to a high. each subsequent new data bit is al so output on the rising edge of sclk (see figure 30). the receiving device should use the falling edge of sclk to latch the data bits. after the 24th sclk, the sdo/rdy output will remain in the st ate of the lsb data bit until a new conversion is completed. at this time, the sdo/rdy will go high if low and then go low to indicate that a new conversion word is available. if not all data bits are read from the sdo/rdy pin prior to the completion of a new conversion, they will be overwritten. sclk should be low during time t 6 , as shown in figure 30, when sdo/rdy is high. if the user wants the sdo/rdy signal to go high after reading the 24 bits of the conversion data word, a 25th sclk can be issued. the 25th sclk will force the sdo/rdy signal to go high and remain high until it falls to signal that a new conversion word is available. figure 31 illustrates the behavior of the sdo/rdy signal when a 25th sclk is used. figure 29. sdo/rdy delay after multiplexer change sdo/rdy table 9. output codes co rresponding to input input signal output code (hex) + 0.5v ref /gain 7fffff (+0.5v ref /gain)/(2 23 - 1) 000001 0 000000 (-0.5v ref /gain)/(2 23 - 1) ffffff - 0.5v ref /gain 800000 figure 30. output data waveforms usin g 24 sclks to read conversion data sdo/rdy data ready data ready data msb lsb new data ready 23 22 21 0 sclk t 4 t 2 1 t 3 24 t5 t 6 t 3 t 7
ISL26132, isl26134 16 fn6954.1 september 9, 2011 offset calibration control the offset internal to the adc can be removed by performing an offset calibration operation. offset calibration can be initiated immediately after reading a conversion word with 24 sclks by issuing two additional sclks. the offset calibration operation will begin immediately after the 26th sclk occurs. figure 32 illustrates the timing details for the offset calibration operation. during offset calibration, the analog inputs are shorted internally and a regular conversion is performed. this conversion generates a conversion word that represents the offset error. this value is stored and used to digitally remove the offset error from future conversion words. the sdo/rdy output will fall to indicate the completion of the offset calibration operation. table 10. interface timing characteristics parameter description min typ max units t 2 sdo/rdy low to first slk 0 ns t 3 sclk pulsewidth, low or high 100 ns t 4 sclk high to data valid 50 ns t 5 data hold after sclk high 0 ns t 6 register update time 39 s t 7 conversion period speed = 1 12.5 ms speed = 0 100 ms figure 31. output data waveforms for sdo/rdy polling new data ready data ready sdo/rdy sclk 23 22 21 0 24 1 25 data 25th sclk forces sdo/rdy high figure 32. offset calibration waveforms data ready after calibration calibration begins sdo/rdy sclk 23 22 21 0 23 24 25 26 1 t 8 figure 33. standby mode waveforms data ready start conversion standby mode sdo/rdy sclk 23 22 21 0 1 24 t 11 t 10 t 9 23 table 11. sdo/rdy delay after calibration parameter min max units t 8 speed = 1 108 109 ms speed = 0 808 809 ms
ISL26132, isl26134 17 fn6954.1 september 9, 2011 standby mode operation the adc can be put into standby mode to save power. standby mode reduces the power to all circuits in the device except the crystal oscillator amplifier. to enter the standby mode, take the sclk signal high and hold it high after sdo/rdy falls. the converter will remain in standby mode as long as sclk is held high. to return to normal operation, take sclk back low and wait for the sdo/rdy to fall to indicate that a new conversion has completed. figure 33 and table 12 illustrate the details of standby mode. supply currents are equal in standby and power-down modes unless a crystal is used. if the crystal is used, the crystal amplifier is turned on, even in the standby mode. performing offset calibration after standby mode to perform an offset calibration automatically upon returning from standby, deliver 2 or more additional sclks following a data read cycle, and then set and hold sclk high. the device will remain in standby as long as sclk remains high. a calibration cycle will begin once sclk is brought low again to resume normal operation. addi tional time will be re quired to perform the calibration after returning from standby. figure 34 and table 13 illustrate the details of performing offset calibration after standby mode. table 12. standby mode timing parameter description min max units t 9 sclk high after sdo/rdy low speed = 1 0 12.44 ms speed = 0 0 99.94 t 10 standby mode delay speed = 1 12.5 speed = 0 100 t 11 sdo/rdy falling edge after sclk low speed = 1 50 60 speed = 0 400 410 table 13. offset calibration timing after standy parameter description min max units t 12 sdo/rdy low after sclk low speed = 1 108 113 ms speed = 0 808 813 ms figure 34. offset calibration waveforms after standby sdo/rdy sclk 23 22 21 21 0 12425 standby mode data ready after calibration 23 begin calibration t 12 t 10
ISL26132, isl26134 18 fn6954.1 september 9, 2011 operation of pdwn pdwn must transition from low to high after both power supplies have settled to specified levels in order to initiate a correct power-up reset (figure 35). this can be implemented by an external controller or a simple rc delay circuit, as shown in figure 36. in order to reduce power consum ption, the user can assert the power-down mode by bringing pdwn low as shown in figure 37. all circuitry is shut down in this mode, including the crystal oscillator. after pdwn is brought high to resume operation, the reset delay varies depending on the clock source used. while an external clock source will re sume operation immediately, a circuit utilizing a crystal will incur about a 20 millisecond delay due to the inherent start-up time of this type of oscillator. figure 35. power-down timing relative to supplies 10s avdd dvdd pdwn figure 36. pdwn delay circuit d vdd 1k 2.2nf connect to pdwn pin figure 37. power-down mode waveforms sdo/rdy sclk t 11 pdwn power-down mode start conversion data ready clk source wakeup t 13 t14 t 14 table 14. power-down recovery timing parameter description typ units t 13 clock recovery after pdwn high internal oscillator 7.95 s external clock source 0.16 s 4.9152mhz crystal oscillator 5.6 ms t 14 pdwn pulse duration 26 s (min)
ISL26132, isl26134 19 fn6954.1 september 9, 2011 applications information power-up sequence ? initialization and configuration the sequence to properly power-up and initialize the device are as follows. for details on individual functions, refer to their descriptions. 1. a vdd , d vdd ramp to specified levels 2. apply external clock 3. pull pdwn high to initiate reset 4. device begins conversion 5. sdo/rdy goes low at end of first conversion optional actions ? perform offset calibration ? place device in standby ? return device from standby ? read on-chip temperature (applicable to ISL26132 only) application examples weigh scale system figure 38 illustrates the ISL26132 connected to a load cell. the a/d converter is configured for a gain of 128x and a sample rate of 10sps. if a load cell with 2m v/v sensitivity is used, the full scale output from the load cell will be 10mv. on a gain of 128x and sample rate of 10sps, the converter noise is 67nv p-p . the converter will achieve 10mv/67nv p-p = 149,250 noise free counts across its 10mv input signal. this equates to 14,925 counts per mv of input signal. if five output words are averaged together this can be improved by 5 to yield 5*14925 counts = 33,370 counts per mv of input signal with an effective update rate of 2 readings per second. thermocouple measurement figure 39 illustrates the ISL26132 in a thermocouple application. as shown, the 4.09 6v reference combined with the pga gain set to 128x sets the input span of the converter to 16mv. this supports the k type thermocouple measurement for temperatures from -270c at -6.485mv to +380c at about 16mv. if a higher temperature is preferred, the pga can be set to 64x to provide a converter span of 32mv. the will allow the converter to support temperature measurement with the k type thermocouple up to about +765c. in the circuit shown, the thermoco uple is referenced to a voltage dictated by the resistor divider from the +5v supply to ground. these set the common mode voltage at about 2.5v. the 5m resistors provide a means for detection of an open thermocouple. if the thermocouple fails open or is not connected, the bias through the 5m resistors will cause the input to the pga to go to full scale. avdd vref+ cap cap ain+1 ain-1 ain+2 ain-2 vref- agnd dgnd temp a0 speed xtalout pdwn sclk sdo/rdy gain0 gain1 dvdd ISL26132 xtalin/clock + - 0.1f vdd micro controller gnd 16 9 10 11 12 14 13 15 17 2, 5, 6 7 8 21 3 4 22 23 24 19 20 gain = 128 3v 5v 0.1f 18 1 figure 38. weigh scale application
ISL26132, isl26134 20 fn6954.1 september 9, 2011 pcb board layout and system configuration the ISL26132,isl26134 adc is a very low noise converter. to achieve the full performance available from the device will require attention to the printed circ uit layout of the circuit board. care should be taken to have a full ground plane without impairments (traces running throug h it) directly under the chip on the back side of the circuit board. the analog input signals should be laid down adjacent (ain+ and ain- for each channel) to achieve good differential signal practice and routed away from any traces carrying active digita l signals. the connections from the cap pins to the off-chip filter capacitor should be short, and without any digital signals nearby. the crystal, if used should be connected with relatively short leads. no active digital signals should be routed near or under the crystal case or near the traces, which connect it to the adc. the agnd and dgnd pins of the adc should be connected to a common solid ground plane. all digital signals to the chip should be powered from the same supply, as that used for dvdd (do not allow digital signals to be active high unless the dvdd supply to the chip is alive). route all active digital signals in a way to keep distance from any analog pin on the device (ain, vref, cap, avdd). power on the avdd supply should be active before the vref voltage is present. pcb layout patterns for the chips (ISL26132 and isl26134) are found on the respective package outline drawings on pages 22, and 23. avdd vref+ ain+1 ain-1 ain+2 ain-2 vref- agnd dgnd temp a0 speed xtalout pdwn sclk sdo/rdy gain0 gain1 dvdd xtalin/clock micro controller 16 11 12 14 13 15 17 2, 5, 6 7 8 21 3 4 22 23 24 19 20 +3v +5v 0.1f 18 1 figure 39. thermocouple measurement application 4.9152 mhz isl21009 4.096v 10nf 1f 10k 10k 0.1f type k 5m 5m
ISL26132, isl26134 21 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6954.1 september 9, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: ISL26132, isl26134 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 09/08/11 fn6954.1 power supply requirements on page 6 - aidd - an alog supply current - normal mode, avdd = 5, gain = 1,2 changed typ and max from ?6, 7.3? to ?7, 8.5? power dissipation, total normal mode, avdd = 5, gain = 1, 2 changed from ?43.3? to ?49.6? mw (max) 08/22/11 fn6954.0 initial release.
ISL26132, isl26134 22 fn6954.1 september 9, 2011 package outline drawing m24.173 24 lead thin shrink small outline package (tssop) rev 1, 5/10 detail "x" typical recommended land pattern top view side view end view dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. dimensions are measured at datum plane h. dimensioning and tolerancing per asme y14.5m-1994. dimension does not include dambar protrusion. allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm. dimension in ( ) are for reference only. conforms to jedec mo-153. 6. 3. 5. 4. 2. 1. notes: 7. 5 seating plane c h 3 2 1 24 b 12 1 3 13 a plane gauge 0.05 min 0.15 max 0-8 0.60 0.15 0.90 1.00 ref 0.25 see detail "x" 0.15 0.25 (0.65 typ) (5.65) (0.35 typ) (1.45) 6.40 4.40 0.10 0.65 1.20 max pin #1 i.d. mark 7.80 0.10 +0.05 -0.06 -0.06 +0.05 -0.10 +0.15 0.20 c b a 0.10 c - 0.05 0.10 c b a m
ISL26132, isl26134 23 fn6954.1 september 9, 2011 package outline drawing m28.173 28 lead thin shrink small outline package (tssop) rev 1, 5/10 detail "x" typical recommended land pattern top view side view end view dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. dimensions are measured at datum plane h. dimensioning and tolerancing per asme y14.5m-1994. dimension does not include dambar protrusion. allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm. dimension in ( ) are for reference only. conforms to jedec mo-153. 6. 3. 5. 4. 2. 1. notes: 7. 5 seating plane c h 3 2 1 28 b 14 1 3 15 a plane gauge 0.05 min 0.15 max 0-8 0.60 0.15 0.90 1.00 ref 0.25 see detail "x" 0.25 (0.65 typ) (5.65) (0.35 typ) (1.45) 6.40 4.40 0.10 0.65 1.20 max pin #1 i.d. mark 9.70 0.10 -0.06 0.15 +0.05 -0.10 +0.15 -0.06 +0.05 0.20 c b a 0.10 c - 0.05 0.10 c b a m

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